1. Field of the Invention
The present invention relates to a method for fabricating field-effect semiconductor devices which having both N- and P-type MISFETs (Metal Insulator Semiconductor Field Effect Transistors) on a common substrate, such as, for example, a complementary-type field-effect semiconductor device.
2. Background Art
Conventionally, two typical types of complementary field-effect semiconductor devices are known. Namely, one comprises N- and P-type MISFETs which are both of the surface-channel type, while the other comprises a surface-channel N-type MISFET and a buried-channel P-type MISFET.
FIG. 64 shows an example of a conventional fabricating technique concerning the latter complementary-type MISFET. In the drawing, a gate electrode of the P-channel MISFET, the polysilicon having the same shape of that of the N-channel MISFET, is adopted. The P-channel MISFET has a buried-channel structure. More specifically, in FIG. 64, the numeral 21 designates the buried-channel layer of the P-channel MISFET.
If the latter technique having the N-type surface-channel and the P-type buried-channel is adopted, there must be an advantage in the fabrication process such that the same N-type polysilicon can be adopted for both gate electrodes (see FIG. 64). However, the buried-channel P-type MISFET is disadvantageous with respect to the current-off characteristics (i.e., subthreshold characteristics), is apt to be affected by the short channel effect, and it is difficult to control the threshold voltage compared with those of the surface-channel type.
On the other hand, the former technique utilizing the surface-channel P-type MISFET is advantageous at smaller scales and at higher-performance levels of the complementary-type field-effect semiconductor device; however, different types of gate electrode material should be utilized for N- and P-type MISFETs respectively. Conventionally, two types of methods for fabricating such a device are known, namely, the complementary-type field-effect semiconductor device having the dual N.sup.+ /P.sup.+ polysilicon gate structure. Hereinafter, the two methods will be referred to as the first method and the second method.
In the first method, the gate electrode materials are independently deposited, whereby independent gate electrode patterns are formed. However, the first method has the following disadvantages. First, lithographic processing with highly accurate pattern dimensions is required to be performed twice. Furthermore, when the gate electrode patterns for P-type and N-type MISFETs are designed, attention must be paid to the layering accuracy, depending on the lithographic technique used. Furthermore, the second gate electrode material is apt to remain on the side wall of the first formed gate electrode, so that two or more times larger degree of over-etching is required for the second gate electrode forming process compared with that of the first process.
Therefore, the following second method has generally been adopted in order to overcome the above problems. Specifically, undoped polysilicon is utilized for gate electrode materials; gate electrode patterns for both N- and P-channel MISFETs are simultaneously formed during one lithographic process; a mask is formed by means of lithography; impurity is doped twice by means of ion implantation; whereby the gate electrode for the P-channel MISFET is formed of P-type polysilicon and that for the N-channel MISFET is formed of N-type polysilicon.
Alternatively, when the deposition of the undoped polysilicon is completed, impurities respectively required for N- and P-channel regions are doped by means of the ion implantation method, the gas-source diffusion method, or the like; and the electrode patterns are formed by only one lithographic process.
According to the above methods, the lithographic process concerning the gate electrode pattern formation can be completed in one process.
However, the above second process has the following problems.
First, if the thickness of the gate insulator film is reduced when the device is scaled down, the doped impurities are apt to pass through the thin gate oxide film and thereby reach the substrate. Therefore, it is difficult to use high temperature impurity diffusion processes for a long time and to sufficiently raise the concentration of the impurity in the gate polysilicons in the vicinity of the interface between the gate insulator and the gate polysilicons. If the concentration of the impurity in the gate polysilicons in the vicinity of interface between the gate insulator and the gate polysilicons is insufficiently increased, it may cause a problem such that when the MISFET is set to the "ON" status, a thick depletion layer will appear in the gate polysilicon, which causes a drop in the current driving capability of the device.
Second, when the distance between the active regions of the N- and P-channel MISFETs are minimized due to scaling down of the device, impurities doped to the respective gate electrodes are apt to diffuse in the polysilicon electrode and to invade the opposite gate electrode. Therefore, the carrier density of the gate polysilicon will drop, and resistance of the device will increase. For stacked film in particular, comprising an upper layer rich in tungsten, the diffusion speed of the doped impurity in the upper layer is 10 or more times higher than that in the other layers, and therefore, a serious problem may result. The carrier density drop not only causes the resistance to increase but also causes increased depletion layer thickness of the gate electrode when the MISFET is set to the "ON" status (see FIG. 65). In FIG. 65, the numeral 22 designates the low-carrier density region.